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datasheet 12-output differential z-bu ffer for pcie gen3 and qpi 9ZX21200 idt? 12-output differential z-buffer for pcie gen3 and qpi 1 9ZX21200 rev d 041513 description the 9ZX21200 is a small-footprint 12-output differential buffer that meets all the performance requirements of the intel db1200z specification. the 9ZX21200 is backwards compatible to pcie gen1 and gen2 applications. a fixed, internal feedback path maintain s low drift for critical qpi applications. in bypass mode, the 9ZX21200 can provide outputs up to 150mhz. recommended application 12-output pcie gen3/ qpi differential buffer for romley and newer platforms key specifications ? cycle-to-cycle jitter <50ps ? output-to-output skew < 65 ps ? input-to-output delay variation <50ps ? pcie gen3 phase jitter < 1.0ps rms ? qpi 9.6gt/s 12ui phase jitter < 0.2ps rms features/benefits ? space-saving 56-pin package ? fixed feedback path for 0ps input-to-output delay ? 9 selectable smbus addresses; mulitple devices can share the same smbus segment ? 4 oe# pins; hardware control of four outputs ? pll or bypass mode; pll can dejitter incoming clock ? 100mhz or 133mhz pll mode operation; supports pcie and qpi applications ? selectable pll bandwidth; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for low emi ? software control of pll bandwidth and bypass settings/pll can dejitter incoming clock (b rev only) output features ? 12 - 0.7v differential hcsl output pairs block diagram logic dif(11:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) dfb_out dif_in dif_in# oe(8,6,4,2)# iref
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 2 9ZX21200 rev d 041513 pin configuration power management table mlf power connections functionality at power-up (pll mode) pll operating mode readback table pll operating mode table tri-level input thresholds 9ZX21200 smbus addressing vdda dif_11# dif_11 dif_10# dif_10 gnd vdd vdd dif_9# dif_9 voe8# dif_8# dif_8 vdd 56 55 54 53 52 51 50 49 48 47 46 45 44 43 gnda 142 gnd iref 241 dif_7# 100m_133m# 340 dif_7 hibw_bypm_lobw 439 voe 6# ckpwrgd_pd# 538 dif_6# gnd 637 dif_6 vddr 736 gnd dif_in 835 vdd dif_in# 934 dif_5# smb_a0_tri 10 33 dif_5 smbdat 11 32 voe 4# smbclk 12 31 dif_4# smb_a1_tri 13 30 dif_4 dfb_out# 14 29 gnd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 dfb_out dif_0 dif_0# dif_1 dif_1# gnd vdd vdd dif_2 dif_2# voe2 # dif_3 dif_3# vdd notes: pins with ^ prefix have internal 120k pullup pins with v prefix have internal 120k pulldown. 9ZX21200 even though the feedback path is fixed, the dfb_out pair still needs a termination network for the part to function. ckpwrgd_pd# dif_in/ dif_in# smbus en bit dif(11:0)/ dif(11:0)# pll state if not in bypass mode 0 x x low/low off 0 low/low on 1 running on running 1 vdd vdd gnd 56 1 analo g pll 7 6 analog input 21,35,50 22,28,43,49 20,29,36,42, 51 dif clocks pin number description 100m_133m# dif_in mhz dif(11:0) 1100.00dif_in 0133.33dif_in hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode le vel v olta ge low <0.8v mid 1.2 2 .2v smb_a1_tri smb_a0_tri sm bus addre ss 0 0 d8 0 m da 01 de m 0 c2 m m c4 m1 c6 10 ca 1m cc 1 1 ce pi n
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 3 9ZX21200 rev d 041513 pin descriptions pin # pin name type description 1 gnda pwr ground pin for the pll core. 2iref out th is pin establishes the reference for the differential current-mode output p airs. it req uires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances re q uire different values. see data sheet. 3 100m_133m# in 3.3v input to select operating frequency see fu nctionality table for definition 4 hi bw_bypm_ lobw# in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for d etails. 5ckpwrgd_pd# in n otifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subseq uent assertions. low enters power down mode. 6 gnd pwr ground pin. 7 vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered a pp ro p riatel y . 8 dif_in in 0.7 v differential true in p ut 9 dif_in# in 0.7 v differential com p lementar y in p ut 10 smb_a0_tri in smbus address bit. this is a tri-leve l input that w orks in conjunction with the smb_a1 to decode 1 o f 9 smbus addresses. 11 smbdat i/o d ata p in of sm bus circuitr y , 5v tolerant 12 smbcl k in c lock p in of smbu s circuitr y , 5v tolerant 13 smb_a1_tri in smbus address bit. this is a tri-leve l input that w orks in conjunction with the smb_a0 to decode 1 o f 9 smbus addresses. 14 dfb_out# out c omplementary half of differential fee dback output, provides feedback signal to the pll for synchronization with in p u t clock to elim inat e p hase error. 15 dfb_out out true half of differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate p hase error. 16 dif_0 out 0.7v differential true clock output 17 dif_0# out 0.7v differential complementary clock output 18 dif_1 out 0.7v differential true clock output 19 dif_1# out 0.7v differential complementary clock output 20 gnd pwr ground pin. 21 vdd pwr power supply, nominal 3.3v 22 vdd pwr power supply, nominal 3.3v 23 dif_2 out 0.7v differential true clock output 24 dif_2# out 0.7v differential complementary clock output 25 voe2# in active low input for enabling dif pair 2. 1 =disable out p uts, 0 = enable out p uts 26 dif_3 out 0.7v differential true clock output 27 dif_3# out 0.7v differential complementary clock output 28 vdd pwr power supply, nominal 3.3v 29 gnd pwr ground pin. 30 dif_4 out 0.7v differential true clock output 31 dif_4# out 0.7v differential complementary clock output 32 voe4# in active low input for enabling dif pair 4 1 =disable outputs, 0 = enable outputs 33 dif_5 out 0.7v differential true clock output 34 dif_5# out 0.7v differential complementary clock output 35 vdd pwr power supply, nominal 3.3v 36 gnd pwr ground pin. 37 dif_6 out 0.7v differential true clock output 38 dif_6# out 0.7v differential complementary clock output 39 voe6# in active low input for enabling dif pair 6. 1 =disable out p uts, 0 = enable out p uts 40 dif_7 out 0.7v differential true clock out p ut 41 dif_7# out 0.7v differential com p lementar y cl ock o ut p ut 42 gnd pwr ground p in. 43 vdd pwr power su pp l y , nominal 3.3 v 44 dif_8 out 0.7v differential true clock out p ut 45 dif_8# out 0.7v differential com p lementar y cl ock o ut p ut 46 voe8# in active low input for enabling dif pair 8. 1 =disable out p uts, 0 = enable out p uts 47 dif_9 out 0.7v differential true clock out p ut 48 dif_9# out 0.7v differential com p lementar y cl ock o ut p ut 49 vdd pwr power su pp l y , nominal 3.3 v 50 vdd pwr power su pp l y , nominal 3.3 v 51 gnd pwr ground pin. 52 dif_10 out 0.7v differential true clock output 53 dif_10# out 0.7v differential complementary clock output 54 dif_11 out 0.7v differential true clock output 55 dif_11# out 0.7v differential complementary clock output 56 vdda pwr 3.3v power for the pll core.
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 4 9ZX21200 rev d 041513 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9ZX21200. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd, vdd a vd d for core logic and pll 4.6 v 1,2 io supply voltage vdd vdd for differential io 4.6 v 1,2 i nput low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsm b smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 o p eration under these conditions is neither im p lied nor g uaranteed. t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input h igh voltage - dif_in v ihd if dif ferential inputs ( sin g le-ended measurement ) 600 800 1150 mv 1 input low voltage - d if_in v il dif dif ferential inputs ( sin g le-ended measurement ) v ss - 300 0300mv1 i nput c ommon mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - d if_in v swing pea k t o pe ak va lue 30 0 1 450 m v 1 input slew rate - dif_in dv/dt measured dif ferentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty c ycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to c ycle j dif in differential measuremen t 0 125 ps 1 1 guaranteed by design and characterization, not 100% t ested in product ion. 2 slew rate measured throu g h +/-75mv window centered around differential zero
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 5 9ZX21200 rev d 041513 electrical characteristics?input/ supply/common output parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 33 150 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.300 1 ms 1,2 input ss modulation frequency f modi n allowable frequency (trian g ular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 412clocks1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 16 300 us 1,3 tfall t f fall time of control inputs 10 ns 1,2 trise t r rise time of control inputs 10 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for the smbus to be active input current 3 time from deassertion until out p uts are >200 mv 4 dif_in input capacitance input frequency
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 6 9ZX21200 rev d 041513 electrical characteristics?dif 0.7v current mode differential outputs electrical characterist ics?current consumption t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 2 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 8 20 % 1, 2, 4 voltage high vhigh 660 705 850 1 voltage low vlow -150 1 150 1 max voltage vmax 725 1150 1 min voltage vmin -300 -22 1 vswing vswing scope averaging off 300 1407 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 309 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 22 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than v_cross absolut e. mv statistical measurement on single-ended signal using oscillosc ope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 412 ? (1%), i ref = 2.7ma. i oh = 6.4 x i ref and v oh = 0.7v @ z o =85 ? differential impedance. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate of clock / fa lling edge rate of clock#. it is measured in a +/-75mv window centered on the average cross point where clock rising meets clock# fa lling. the median cross point is used to calculate the voltage thresholds the oscillosc ope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes i ddvdd 133mhz, c l = full load; vdd rail, zo=85 ? 260 275 ma 1 i ddvdda 133mhz, c l = full load; vdd rail, zo=85 ? 13 20 ma 1 i ddvddpd power down, vdd rail, zo=85 ? 2 6ma1 i ddvddapd power down, vdd rail, zo=85 ? 1.3 2ma1 1 guaranteed by design and characterization, not 100% tested in production. operating current powerdown current
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 7 9ZX21200 rev d 041513 electrical characteristics?skew and differential jitter parameters t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 25c, 3.3v -100 29 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 2.5 3.7 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across volta g e and temperature -50 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across voltage and temperature -250 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 2.9 5 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 14 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 32 65 ps 1,2,3,8 pll jitter peaking j p eak-hibw lobw#_bypass_hibw = 1 0 1.8 2.5 db 7,8 pll jitter peaking j p eak-lobw lobw#_bypass_hibw = 0 0 0.7 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3.1 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.1 1.4 mhz 8,9 duty cycle t d c measured differentially, pll mode 45 49.6 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 -0.2 2 % 1,10 pll mode 15.7 50 ps 1,11 additive jitter in bypass mode 0.1 50 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter pe aking. 8. guaranteed by desi g n and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross-point to differential cross-point. this parameter can be tuned with external feedback path, if present. 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value.
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 8 9ZX21200 rev d 041513 electrical characteristi cs?phase jitter parameters differential output terminations t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 32 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.8 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.9 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.45 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.20 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.14 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.12 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 0.10 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.13 0.1 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.10 0.5 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.10 0.2 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.09 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.09 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.09 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 5 calculated from intel-supplied clock jitter tool v 1.6.4 2 see http://www.pcisig.com for complete specs additive phase jitter, bypass mode t jphpcieg2 t jphqpi_smi t jphqpi_smi phase jitter, pll mode t jphpcieg2 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final radification by pci sig. dif zo=85ohms,10" rp rp hcsl output buffer 9ZX21200 differential test loads rs rs 2pf 2pf dif zo ( ? )iref ( ? )rs ( ? )rp ( ? ) 100 475 33 50 85 412 27 42.2 or 43.2
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 9 9ZX21200 rev d 041513 clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled 1 cl oc k 1us 0.1s 0.1s 0.1s 1us 1 cloc k -c2c jitter absper min -ssc short-term average min - ppm long-term av erage min 0 ppm per iod nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 dif measurement window units notes ssc off center freq. mh z 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by desi g n and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven by cpu output of main clock, 133 mhz pll mode or bypass mode measurement window units ssc on center freq. mhz 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the 9ZX21200 itself does not contribute to ppm error. dif notes
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 10 9ZX21200 rev d 041513 general smbus serial interf ace information for 9ZX21200 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 11 9ZX21200 rev d 041513 smbustable: pll mode, and frequency select register pin # name control function t yp e 0 1 default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll b w r w hw latch s/w control 0 bit 2 pll mode 1 pll o p eratin g mode 1 r w 1 bit 1 pll mode 0 pll o p eratin g mode 1 r w 1 bit 0 100m_133m# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control register pin # name control function t yp e 0 1 default bit 7 dif_7_en out p ut control overrides oe# p in r w 1 bit 6 dif_6_en out p ut control overrides oe# p in r w 1 bit 5 dif_5_en out p ut control overrides oe# p in r w 1 bit 4 dif_4_en out p ut control overrides oe# p in r w 1 bit 3 dif_3_en out p ut control r w 1 bit 2 dif_2_en out p ut control r w 1 bit 1 dif_1_en out p ut control r w 1 bit 0 dif_0_en out p ut control r w 1 smbustable: output control register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 dif_11_en out p ut control r w 1 bit 2 dif_10_en out p ut control r w 1 bit 1 dif_9_en out p ut control r w 1 bit 0 dif_8_en out p ut control r w 1 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved see pll operating mode readback table reserved reserved reserved reserved b y te 3 b y te 4 b y te 0 3 3 23/24 18/19 16/17 2 b y te 1 53/52 b y te 2 38/37 34/35 30/29 25/26 48/47 42/41 55/54 46/45 reserved reserved reserved reserved reserved reserved reserved reserved enable reserved reserved reserved reserved low/low enable reserved reserved reserved reserved reserved low/low these bits available in b rev onl y . see pll operating mode readback table
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 12 9ZX21200 rev d 041513 smbustable: vendor & revision id register pin # name control function t yp e0 1default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbustable: device id pin # name control function t yp e0 1default bit 7 r1 bit 6 r1 bit 5 r0 bit 4 r0 bit 3 r1 bit 2 r0 bit 1 r0 bit 0 r0 smbustable: byte count register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 r w 0 bit 3 bc3 r w 1 bit 2 bc2 r w 0 bit 1 bc1 r w 0 bit 0 bc0 r w 0 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved 1200 is 200 decimal or c8 hex device id 7 ( msb ) reserved device id 5 device id 6 - b y te 5 - b y te 6 reserved b y te 7 - - - - reserved 0001 for idt/ics reserved - - - - - - - - default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. - reserved reserved writing to this register configures how many bytes will be read back. device id 0 reserved reserved reserved device id 3 - reserved - b y te 8 - - - - device id 2 device id 1 device id 4 revision id a rev = 0000 b rev = 0001 vendor id
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 13 9ZX21200 rev d 041513 common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs (100 ohm differential traces) 33 ohm 1 rs (85 ohm differential traces) 27 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 14 9ZX21200 rev d 041513 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 15 9ZX21200 rev d 041513 package outline and package dimensions (56-pin vfqfpn) ordering information "lf" suffix to the part number designates pb-free configuration, rohs compliant. ?a? and ?b? are the device revisi on designators (will not correlat e with the data sheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. dimensions (mm) symbol min max a0.81.0 a1 0 0.05 a3 0.25 reference b 0.18 0.3 e 0.50 basic d x e basic 8.00 x 8.00 d2 min./max. 4.35 4.65 e2 min./max. 5.05 5.35 l min./max. 0.3 0.5 n56 n d 14 n e 14 anvil singulation -- or -- sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 part / order number shipping package package temperature difference 9ZX21200aklf trays 56-pin vfqfpn 0 to +70c 9ZX21200aklft tape and reel 56-pin vfqfpn 0 to +70c 9ZX21200bklf trays 56-pin vfqfpn 0 to +70c 9ZX21200bklft tape and reel 56-pin vfqfpn 0 to +70c w/o byte 0 pll control with byte 0 pll mode control
9ZX21200 12-output differential z-buffer for pcie gen3 and qpi idt? 12-output differential z-buffer for pcie gen3 and qpi 16 9ZX21200 rev d 041513 revision history rev. issue date issuer description page # a 9/13/2011 rdw 1. updated electrical tables with char data 2. fixed minor typographical errors 3. moved to final various b 12/8/2011 rdw 1. added b rev functionality description to features, benefits 2. updated tdspo_byp parameter from +/-350ps to +/-250ps 3.updated smbus byte 0 with b rev functionality 4. updated ordering information to include b rev 1,7,11,15 c 4/18/2012 rdw 1. updated power connections table to be consistent with 9zxl1230 2. updated rp values on output terminations table from 43.2 ohms to 42.2 or 43.2 ohms to be consistent with intel. 2,8 d 4/15/2013 rdw corrected typo in oe# latency parameter; changed 1 min. to 3 max. cycles to 4 min. to 12 max. clocks. 5
? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp pcclockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com 9ZX21200 12-output differential z-buffer for pcie gen3 and qpi synthesizers

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